Researchers have designed a CMOS-based chip to integrate silicon quantum dots and multiplexed readout electronicsPublished Date: February 14, 2022 |
Recently, the researchers of Ecole Polytechnique Federale de Lausanne (EPFL) and Hitachi Cambridge Laboratory have designed an integrated circuit to integrate silicon quantum dots and multiplexed readout electronics. The chip is based on 40-nm cryogenic complementary metal-oxide-semiconductor (CMOS) technology that is readily and commercially available.
Ruffino and his colleagues at EPFL joined forces with the team at the Hitachi Cambridge Laboratory with the common goal of unifying classical circuits and quantum devices on a single chip. Their paper builds on some of their previous efforts, including the proposal of cryogenic CMOS ICs for quantum computing, as well as the realization of fast-sensing and time-multiplexed sensing of silicon quantum devices.
The primary objective of the recent study was to combine fast-sensing and time-multiplexing techniques devised by the team in Hitachi Lab to achieve two-dimensional multiplexing sensing.
The designed chip is made by CMOS transistors which are similar to those used to make smartphones and other common electronic devices. Unlike conventional transistors, the ones integrated inside the new chip operate at cryogenic temperatures and also contain an array of silicon quantum dots.
The unique design employed by Ruffino and his colleagues allows their chip to simultaneously read multiple quantum devices connected to a single wire and at different frequencies. In addition, the devices to be read can be selected individually by means of access transistors.
A major advantage of this chip is that its two modules (i.e., device and sensing module) are combined using standard and commercially available 40nm CMOS technology. This means that it can easily be made on a large scale in the future.
In future, the unique architecture introduced by this team of researchers could be used to read out large 2D arrays of silicon quantum dots. Ultimately, this may help address some scaling-related limitations of existing silicon quantum processors.